1. Field of the Invention
The present invention relates to a method for making a semiconductor device of high integration, high speed and high accuracy. More particularly, the present invention relates to an improved method for making semiconductor devices comprising vertical bipolar transistors formed with high integration, designed for high speed operation and manufactured with high accuracy for stable performance.
2. Description of the Prior Art
Recently, semiconductor devices have been developed to have even higher integration and high speed operation, and transistors with self-aligned contact are necessary. In order to fulfill these requirements, the emitter part is structured in the self-aligned configuration by utilizing an antioxidation film, and forming the emitter and the base by ion-implantation is adopted in the conventional manufacturing process. The above-mentioned conventional process is described with reference to the appended FIG. 1(A), FIG. 1(B), FIG. 1(C), FIG. 1(D), FIG. 1(E) and FIG. 1(F).
Firstly, on a principal surface of an n-type silicon substrate 1, a SiO.sub.2 film 2 is formed with a thickness of about 4000 .ANG. by, for instance, a known oxidation process, and an opening is formed on the part to become the base region, as shown in FIG. 1(A).
Then, a polycrystalline silicon film 3 of about 2000 .ANG. in thickness is deposited thereon, and As-ions are implanted with a density of 7.times.10.sup.15 ions/cm.sup.2 with a 130 KeV acceleration energy. Under this condition, the As-ions are injected in the polycrystalline silicon film 3 as shown in FIG. 1(B). Thereafter, an Si.sub.3 N.sub.4 film 4 is deposited over all of the substrate to a thickness of about 500 .ANG., as shown in FIG. 1(C).
Then, a resist 5 of a desired pattern is formed on a part of the structure to make the emitter part, and by utilizing the resist film 5 as a mask, the Si.sub.3 N.sub.4 film 4 and polycrystalline silicon film 3 surrounding the area adjacent to the resist film 5 are etched. And further, by utilizing the resist 5 and the underlying oxide mask 2 as mask, the surface part of the substrate 1 is further etched by about 0.2 .mu.m from the level of the substrate surface as shown in FIG. 1(D). At this time, since the polycrystalline silicon film 3 containing As has a very large etching rate, the polycrystalline silicon part under the Si.sub.3 N.sub.4 film 4 is etched to form an oblique face.
Next, the resist film 5 is removed by a known method, and by utilizing the Si.sub.3 N.sub.4 film 4 as a mask an oxidation is carried out to form an oxide film 6 of about 1500 .ANG. in thickness. Since the upper surface of the polycrystalline silicon film 3 is covered by the Si.sub.3 N.sub.4 film 4, the upper surface of the polycrystalline silicon film 3 is not oxidized. Thereafter, boron ions are implanted with a density of 1.2.times.10.sup.15 ions/cm.sup.3 by an acceleration energy of 60 KeV, followed by a thermal treatment at 900.degree. C. for about 30 min., to form an active base region 7 and inactive bases 8, 8. By the thermal treatment, the As in the polycrystalline silicon film 3 is diffused into the substrate 1, and therefore n-type emitter region 9 is formed, as shown in FIG. 1(E).
In the above-mentioned configuration, defects induced by ion implantation are formed as shown by broken lines 10 in the polycrystalline silicon film 3 and in the inactive base regions (8, 8).
Thereafter, the Si.sub.3 N.sub.4 film 4 is removed by a known method, and a contact opening is formed on the inactive base region 8. An emitter electrode 11 and a base electrode 12 are formed as shown in FIG. 1(F). Thus, a conventional semiconductor device with a vertical bipolar transistor is completed. The above-mentioned conventional transistor has the following advantages:
(1) A high integration is achieved by use of the selfalignment of the emitter and the emitter contact. PA0 (2) Since the side faces of the emitter region have no PN junction, there is no likelihood of an adverse elongation of transit time induced by the carved shape of the junction of the base-emitter, accordingly an excellent high frequency performance is achievable. PA0 (3) Base resistance is small, since the active base region is connected at the part of highest concentration of the inactive base regions. PA0 (1) A high integration is attainable as a result of self-alignment between the emitter region and the emitter contact. PA0 (2) Since the active base region and the emitter regions are formed by ion implantation, there is substantially no scattering of h.sub.FE. PA0 (1) When the seat resistance required for the inactive base region 57 is selected to be 300 .OMEGA./.quadrature., the polycrystalline silicon film 53 must have boron concentration of 10.sup.15 /cm.sup.2 and a thickness of about 3000 .ANG., and furthermore, the CVD SiO.sub.2 insulation film 54 used as the mask to form the high concentration emitter 59 must be 3000 .ANG. thick. Accordingly, the thickness difference at the opening part 55 becomes at least 6000 .ANG., and as a consequence the lead wires are likely to be put off during the electrode formation thereon. PA0 (2) Since there is a need to completely remove the polycrystalline silicon film 53 containing the boron, an overetching must be made, thereby to slightly etch the surface of the substrate 51, and therefore the above-mentioned level difference becomes even greater. PA0 (3) Since the inactive base regions 57 are formed by diffusion of impurity from the CVD polycrystalline silicon film 53, the base resistance thereof is large.
In the above-mentioned conventional example, however, the polycrystalline silicon film 3 contains As as an impurity, and when etching the polycrystalline silicon film 3 and the substrate 1 as shown in FIG. 1(D), the polycrystalline silicon film 3 under the Si.sub.3 N.sub.4 film 4 is caused to have an oblique wall. Accordingly, when boron ions are implanted after forming the oxide film 6, the defect formed by the ion implantation crosses the emitter-base junction as shown by dotted line 10 in FIG. 1, thereby allowing the possibility of producing a leak current between the emitter and the base regions. Because of such a leak current, the h.sub.FE is likely to have scatterings and accordingly, a highly reliable, accurate transistors cannot be obtained.
In order to improve the above-mentioned problem, there is a proposal disclosed in 1980 in an IEDM (International Electron Devices Meeting) wherein a polycrystalline silicon base is used to form the active base and the emitter by an ion implantation process, which is hereafter described with reference to FIG. 2(A), FIG. 2(B), FIG. 2(C) and FIG. 2(D). Firstly, as shown in FIG. 2, on an n-type substrate 51, an insulation oxide film 52 is selectively formed, and thereafter a boron-doped polycrystalline silicon film 53 and further thereon a CVD SiO.sub.2 film 54 are sequentially formed.
By utilizing a resist as a mask in RIE (reactive ion etching), the CVD SiO.sub.2 54 and the underlying polycrytalline silicon film 53 are partly removed. Thereafter, by using wet etching the boron-doped polycrystalline silicon film 53 is removed, to form an opening 55 as shown in FIG. 2(B).
Thereafter, by forming oxide film 56 by utilizing a thermal oxidation or CVD method, and by subsequent thermal treatment, boron is introduced to the substrate 51 from the polycrystalline silicon film 53, thereby forming inactive base region 57 as shown in FIG. 2(C).
Then, by another RIE, the oxide film 56 in the opening of the substrate is removed, and thereafter by means of ion implantation, an active base 58 and an emitter region 59 are formed as shown in FIG. 2(D).
The above-mentioned second conventional process has the following advantages:
However, the above-mentioned conventional process has the following shortcomings.